G430 LE6, LENOVO IBM

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LE6 BLOCK DIAGRAM
01
PCB STACK UP
6L
LAYER 1 : TOP
CPU
Penryn
CPU THERMAL
SENSOR
LAYER 2 : GND
14.318MHz
PAGE 6
A
A
LAYER 3 : IN1
LAYER 4 : IN2
LAYER 5 : VCC
478P (uPGA)/35W
PAGE 4,5
CLK_CPU_BCLK,CLK_CPU_BCLK#
CLK_MCH_BCLK,CLK_MCH_BCLK#
DREFCLK,DREFCLK#
DREFSSCLK,DREFSSCLK#
CLOCK GEN
ALPRS355B MLF64PIN
FSB 667/800/1066
PAGE 3
LAYER 6 : BOT
NORTH BRIDGE
DDRII-SODIMM1
DDRII 667/800 MHz
PAGE 12,13
Cantiga
CRT
DDRII-SODIMM2
DDRII 667/800 MHz
B
B
PAGE 18
PAGE 12,13
PAGE 7,8,9,10,11
Dual Link
LCD CONN
32.768KHz
PAGE 18
DMI LINK
NBSRCCLK, NBSRCCLK#
SYSTEM DISCHARGER
SATA0 150MB
USB2.0
SATA - HDD
PAGE 28
PAGE 25
SOUTH BRIDGE
USB2.0 Ports
BlueTooth
CCD
PAGE 26
PAGE 26
PAGE 25
SATA4 150MB
X3
SYSTEM CHARGER(ISL6251AHAZ-T)
SATA - CD-ROM
PAGE 25
PAGE 29
ICH-9M
PCI-E
X1
X1
X1
DDR II SMDDR_VTERM
1.8V/1.8VSUS(TPS51116REGR)
X1
Azalia
C
C
PAGE 30
PAGE 14,15,16,17
Mini PCI-E
Card
LAN
Express
Card
(NEW CARD)
J Micro 385
BROADCOM
BCM 5906M
AUDIO
CODEC
VCCP +1.5V AND GMCH
1.05V(RT8204)
(Wireless
LAN )
(10/100 LAN)
PAGE 19
LPC
32.768KHz
CX20561-12Z
PAGE 25
PAGE 31
MDC CONN
PAGE 25
PAGE 20
PAGE 21
PAGE 21
CPU CORE ISL6266A
Keyboard
25MHz
RJ45
PAGE 20
PAGE 32
PAGE 23
AUDIO
Amplifier
TPA6017A2
Touch Pad
ITE
8502E-L
Memory
CardReader
PAGE 24
PAGE 22
SYSTEM POWER ISL6237IRZ-T
PAGE 33
PAGE 19
microphone
Audio Jacks
Jack to
Speaker
PAGE 22
D
D
(Phone/ MIC)
PAGE 21
PAGE 22
GMT G9931P1U
SPI
PAGE 24
PROJECT : LE6
Quanta Computer Inc.
PROJECT : LE6
Quanta Computer Inc.
PROJECT : LE6
Quanta Computer Inc.
FAN
PAGE 23
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Custom
Custom
Custom
BLOCK DIAGERAM
Wednesday, April 23, 2008
BLOCK DIAGERAM
Wednesday, April 23, 2008
BLOCK DIAGERAM
Wednesday, April 23, 2008
1A
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1A
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Date:
Date:
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02
Board Stack up Description
PCB Layers
Voltage Rails
Layer 1
TOP
Voltage Rails
ON S0~S2
ON S3
ON S4
ON S5
Control signal
Layer 2
GND
VCC_CORE
X
VRON
+1.5V
+1.05V
X
MAINON
Layer 3
IN1
X
MAINON
Layer 4
IN2
5V_S5/3V_S5/1.5V_S5
X
X
X
X
S5_ON
D
D
Layer 5
Layer 6
SVCC
BOTTOM
5VSUS/3VSUS/1.8VSUS
X
X
SUSON
SMDDR_VTERM/+2.5V/+3V/+5V/+12V
X
MAINON
+VCC_GFX_CORE/+1.2V_GFX_PCIE
X
MAINON
LANVCC
X
X
X
X
LAN_ON
Power On Sequencing Timing Diagram
3VPCU
X
X
X
X
VL
5VPCU
X
X
X
X
VL
VID
VRON
Tsft_star_vcc
Vboot
Vid
VCC_CORE
Tboot
Tboot-vid-tr
CPU_UP
Tcpu_up
Vccp
Vccp_UP
Tvccp_up
Vccgmch
ACIN POWER ON TIMING
GMCHPWRGD
Tgmch_pwrgd
ACIN
PCI DEVICE
IDSEL#
REQ# / GNT#
Interrupts
CLK_ENABLE#
5VPCU/3VPCU
RICOH832
AD25
REQ0# / GNT0#
INT E#/F#
IMVP4_PWRGD
Tcpu_pwrgd
NBSWON#
C
C
To ICH7
DNBSWON#
YONAH Power-up Timing Specifications
S5_ON
To ICH7
Td
RSMRST#
RESET#
From ICH7
SUSB#,SUSC#
SUSON
From 97551
BCLK
From 97551
MAINON
Tc
VSUS,VCC
From 97551
Te
PWRGOOD
VRON
+1.5V/+1.05V
Tf
Ta
Tb
VCC_CORE
VCC
Vcc,boot
To clock generator
CLK_EN#
VID[5:0]
99ms < t 214
PWROK
To GMCH/other PCI device
PLTRST#\PCIRST#
B
B
VCCP
Ta=VCC and VCCP asseration to VID[5:0] vaild
Tb=VID[5:0] stable to VCC vaild
Tc=BCLK stable to PWRGOOD assertion
Td=PWRGOOD to RESET# de-assertion time
Te=Vcc,boot vaild to PWRGOOD assertion time
A
A
PROJECT : LE6
Quanta Computer Inc.
PROJECT : LE6
Quanta Computer Inc.
PROJECT : LE6
Quanta Computer Inc.
Size
Date:
Size
Date:
Size
Date:
Document Number
Document Number
Document Number
Rev
Rev
Rev
Custom
Custom
Custom
SYSTEM INFORMATION
Friday, May 02, 2008
SYSTEM INFORMATION
Friday, May 02, 2008
SYSTEM INFORMATION
Friday, May 02, 2008
1A
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3
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7
8
03
+3V
+3V
L55
BLM18PG181SN1_6
Y2
Y2
+CK_VDD_MAIN
1
2
CG_XIN
CG_XOUT
1
2
180 ohms@100Mhz
C260
10U/6.3V/X5R_8
14.318MHZ+/- 10ppm
14.318MHZ+/- 10ppm
Q11
2N7002E
Q11
2N7002E
3
R164
10K_6
R196
10K_6
C539
0.1U/10V/X7R_4
C540
0.1U/10V/X7R_4
C261
0.1U/10V/X7R_4
C266
0.1U/10V/X7R_4
C538
0.1U/10V/X7R_4
C282
33P/50V/NPO_4
C288
33P/50V/NPO_4
CGDAT_SMB
1
(16,26)
PDAT_SMB
14.318MHz
A
A
L54
BLM18PG181SN1_6
+3V
+CK_VDD_MAIN2
1
2
Q12
2N7002E
Q12
2N7002E
3
180 ohms@100Mhz
+3V
C515
10U/6.3V/X5R_8
C534
C534
C533
C533
C520
C520
C521
C521
C522
C522
C535
0.1U/10V/X7R_4
CGCLK_SMB
1
(16,26)
PCLK_SMB
CLK_MCH_OE#
R221
R221
10K_4
10K_4
2
1
0.1U/10V/X7R_4
0.1U/10V/X7R_4
0.1U/10V/X7R_4
0.1U/10V/X7R_4
0.1U/10V/X7R_4
0.1U/10V/X7R_4
0.1U/10V/X7R_4
0.1U/10V/X7R_4
0.1U/10V/X7R_4
0.1U/10V/X7R_4
NEW-CARD_CLK_REQ#
R180
R180
10K_4
10K_4
internal have
already build-in
33ohm damping
resisteor
2
1
PCIE_LANREQ#
R213
R213
10K_4
10K_4
2
1
L35
L35
VDDCPU
U8
U8
1
2
+CK_VDD_MAIN
2
48
VDD_PCI
NC
BLM18PG181SN1_6
BLM18PG181SN1_6
9
VDD_48
C257
10U/6.3V/X5R_8
CGCLK_SMB
16
64
CGCLK_SMB (12,13,26)
CGDAT_SMB (12,13,26)
VDD_PLL3
SCLK
C262
0.1U/10V/X7R_4
CGDAT_SMB
61
63
VDD_REF
SDA
CK505
CK505
PM_STPPCI#
39
38
VDD_SRC
PCI_STOP#
PM_STPPCI# (16)
VDDCPU
PM_STPCPU#
55
37
VDD_CPU
CPU_STOP#
PM_STPCPU# (16)
+3V
+CK_VDD_MAIN2
CLK_CPU_BCLK
12
54
CLK_CPU_BCLK
(4)
VDD_96_IO
CPU0
20
53
CLK_CPU_BCLK#
CLK_CPU_BCLK#
(4)
VDD_PLL3_IO
CPU0#
26
VDD_SRC_IO_1
CLK_MCH_BCLK
51
CPU1
CLK_MCH_BCLK
(7)
CLK_MCH_BCLK#
36
50
VDD_SRC_IO_2
CPU1#
CLK_MCH_BCLK#
(7)
+3V
49
VDD_CPU_IO
B
R215
10K_4
CPU_ITP
B
45
47
T8
T8
VDD_SRC_IO_3
SRC8/ITP
*PAD
*PAD
EB1213-0001
46
CPU_ITP#
*PAD
*PAD
SRC8#/ITP#
T9
T9
R197
R197
33_4
33_4
R_PCI_CLK_8502
CLK_PCIE_NEW#
1
35
(25)
PCI_CLK_8502
PCI0/CR#_A
SRC10#
CLK_PCIE_NEW#
(26)
PCLK_MINI_LPC
CLK_PCIE_NEW
34
CLK_PCIE_NEW
(26)
SRC10
R231
*10K_4
PCIE_LANREQ#
R214
R214
475/F_4
475/F_4
LANREQ#
3
(21)
PCIE_LANREQ#
PCI1/CR#_B
NEW-CARD_CLK_REQ#_R
CLK_3GPLLREQ#_R
R176
R176
475/F_4
475/F_4
NEW-CARD_CLK_REQ#
33
NEW-CARD_CLK_REQ#
(26)
SRC11/CR#_H
PCLK_MINI_LPC
CLK_MCH_OE#
R217
R217
33_4
33_4
4
32
R207
R207
475/F_4
475/F_4
(26)
PCLK_LPC_DEBUG
PCI2/TME
SRC11#/CR#_G
CLK_MCH_OE#
(8)
R216
*4.7K_4
FCTSEL1
R218
R218
*33_4
*33_4
CLK_PCIE_3GPLL
CLK_PCIE_3GPLL#
5
30
*PAD
*PAD
T38
T38
PCI3
SRC9
CLK_PCIE_3GPLL
(8)
EB1213-0002
31
CLK_PCIE_3GPLL#
(8)
SRC9#
R219
R219
*33_4
*33_4
FCTSEL1
6
*PAD
*PAD
T39
T39
PCI4/27MHz_Select
R232
10K_4
CLK_PCIE_CARD
44
CLK_PCIE_CARD
(20)
SRC7/CR#_F
R220
R220
33_4
33_4
ITP_EN
CLK_PCIE_CARD#
7
43
(15)
PCLK_ICH
PCIF5/ITP_EN
SRC7#/CR#_E
CLK_PCIE_CARD#
(20)
CG_XIN
CLK_PCIE_ICH
EB1213-0003
60
41
XTAL_IN
SRC6
CLK_PCIE_ICH
(15)
CLK_PCIE_ICH#
40
CLK_PCIE_ICH#
(15)
SRC6#
CG_XOUT
59
XTAL_OUT
0=overclocking
of CPU and
SRC Allowed
0=UMA
27
CLK_PCIE_LAN
CLK_PCIE_LAN#
CLK_PCIE_LAN
(21)
SRC4
1 = External VGA
CLK_48M_USB
R208
R208
33_4
33_4
FSA
10
28
(16)
CLK_48M_USB
USB_48/FSA
SRC4#
CLK_PCIE_LAN#
(21)
CPU_BSEL0
R223
R223
2.2K_4
2.2K_4
EB1213-0004
CPU_BSEL1
R162
R162
2.2K_4
2.2K_4
FSB
CLK_PCIE_MINI_
57
24
FSB/TEST/MODE
SRC3/CR#_C
CLK_PCIE_WLAN
(26)
CLK_PCIE_MINI_#
25
CLK_PCIE_WLAN#
(26)
SRC3#/CR#_D
CPU_BSEL2
R161
R161
10K_4
10K_4
FSC
62
REF0/FSC/TESTSEL
1 = overclocking
of CPU and SRC
not Allowed
+3V
CLK_14M_ICH
R160
R160
33_4
33_4
21
CLK_PCIE_SATA
CLK_PCIE_SATA#
(16)
CLK_14M_ICH
SRC2/SATA
CLK_PCIE_SATA
(14)
8
22
VSS_PCI
SRC2#/SATA#
CLK_PCIE_SATA#
(14)
Enable ITP
11
VSS_48
DREFSSCLK
15
17
DREFSSCLK
(8)
VSS_IO
SRC1/SE1/27MHz_NonSS
R233
*10K_4
DREFSSCLK#
19
18
DREFSSCLK#
(8)
VSS_PLL3
SRC1#/SE2/27MHz_SS
52
VSS_CPU
C592
C592
*33P/50V/NPO_4
*33P/50V/NPO_4
CLK_48M_USB
DREFCLK
C
23
13
C
VSS_SRC1
SRC0/DOT96
DREFCLK
(8)
DREFCLK#
EB1213-0005
29
14
VSS_SRC2
SRC0#/DOT96#
DREFCLK#
(8)
ITP_EN
C311
C311
*33P/50V/NPO_4
*33P/50V/NPO_4
PCI_CLK_8502
42
VSS_SRC3
58
56
CK_PWG
(16)
VSS_REF
CKPWRGD/PWRDWN#
C302
C302
*33P/50V/NPO_4
*33P/50V/NPO_4
FCTSEL1
ITP_EN
PCLK_LPC_DEBUG
CLK_14M_ICH
ICS9LPRS365AGLFT/SLG8SP512
ICS9LPRS365AGLFT/SLG8SP512
C303
C303
*33P/50V/NPO_4
*33P/50V/NPO_4
R234
10K_4
C310
C310
*33P/50V/NPO_4
*33P/50V/NPO_4
C255
C255
*33P/50V/NPO_4
*33P/50V/NPO_4
for EMI
GCLK_SEL = FCTSEL1
FCTSEL1
(PIN6)
PIN13
PIN14
PIN24
PIN25
CPU Clock select
FSC
FSB
FSA
CPU
SRC
PCI
0=UMA
DREFCLK
DREFCLK#
SRCT1/LCDT_100
SRCT1/LCDT_100
1
0
1
100
100
100
100
100
33
CPU_BSEL0
R230
R230
0_4
0_4
(4)
CPU_BSEL0
MCH_BSEL0
(8)
0
0
0
0
0
1
133
33
33
33
33
1
1
166
200
266
333
400
R239
R239
1K_4
1K_4
1
0
CPU_BSEL1
R423
R423
0_4
0_4
(4)
CPU_BSEL1
MCH_BSEL1
(8)
0
0
0
100
D
D
1
0
100
100
100
33
R152
R152
1K_4
1K_4
+1.05V
1
1
0
33
33
CPU_BSEL2
R425
R425
0_4
0_4
(4)
CPU_BSEL2
MCH_BSEL2
(8)
1
1
1
RSVD
PROJECT : LE6
Quanta Computer Inc.
PROJECT : LE6
Quanta Computer Inc.
PROJECT : LE6
Quanta Computer Inc.
<FAE>
1K to NB only when
XDP is implement.No
XDP can use 0 ohm
R151
R151
1K_4
1K_4
+1.05V
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Custom
Custom
Custom
CLOCK GENERATOR
Friday, May 02, 2008
CLOCK GENERATOR
Friday, May 02, 2008
CLOCK GENERATOR
Friday, May 02, 2008
1A
1A
1A
Date:
Date:
Date:
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2
1
(3,5,7,8,10,11,14,17,29,32,33)
+1.05V
04
U24A
U24A
(7)
H_A#[35:3]
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
J4
H1
A[3]#
ADS#
H_ADS#
(7)
(7)
H_D#[63:0]
U24B
U24B
H_D#[63:0]
L5
E2
A[4]#
BNR#
H_BNR#
(7)
H_D#0
H_D#1
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
L4
G5
E22
Y22
H_BPRI#
(7)
A[5]#
BPRI#
D[0]#
D[32]#
K5
F24
AB24
A[6]#
D[1]#
D[33]#
M3
H5
H_D#2
H_D#3
E26
V24
A[7]#
DEFER#
H_DEFER#
(7)
D[2]#
D[34]#
N2
F21
G22
V26
A[8]#
DRDY#
H_DRDY#
(7)
D[3]#
D[35]#
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
J1
E1
F23
V23
A[9]#
DBSY#
H_DBSY#
(7)
D[4]#
D[36]#
D
D
N3
G25
T22
A[10]#
D[5]#
D[37]#
P5
F1
E25
U25
HBREQ#0
(7)
A[11]#
BR0#
D[6]#
D[38]#
P2
E23
U23
A[12]#
D[7]#
D[39]#
L2
D20
H_IERR#
R36
R36
56.2/F_4
56.2/F_4
K24
Y25
+1.05V
A[13]#
IERR#
D[8]#
D[40]#
P4
B3
G24
W22
A[14]#
INIT#
H_INIT#
(14)
D[9]#
D[41]#
P1
J24
Y23
A[15]#
D[10]#
D[42]#
R1
H4
J23
W24
H_LOCK#
(7)
A[16]#
LOCK#
D[11]#
D[43]#
H_D#12
H_D#13
H_D#14
H_D#15
H_D#44
H_D#45
H_D#46
H_D#47
M1
H22
W25
(7)
H_ADSTB#0
H_CPURST#
(7)
ADSTB[0]#
D[12]#
D[44]#
C1
F26
AA23
(7)
H_REQ#[4:0]
RESET#
D[13]#
D[45]#
H_REQ#0
H_RS#0
K3
F3
K22
AA24
REQ[0]#
RS[0]#
D[14]#
D[46]#
H_REQ#1
H_REQ#2
H_RS#1
H_RS#2
H2
F4
H23
AB25
REQ[1]#
RS[1]#
D[15]#
D[47]#
K2
G3
J26
Y26
H_RS#[2:0]
(7)
REQ[2]#
RS[2]#
(7)
H_DSTBN#0
DSTBN[0]#
DSTBN[2]#
H_DSTBN#2
(7)
H_REQ#3
H_REQ#4
J3
G2
H26
AA26
H_TRDY#
(7)
(7)
H_DSTBP#0
H_DSTBP#2
(7)
REQ[3]#
TRDY#
DSTBP[0]#
DSTBP[2]#
L1
H25
U22
(7)
H_DINV#0
H_DINV#2
(7)
REQ[4]#
DINV[0]#
DINV[2]#
H_A#[35:3]
G6
HIT#
H_HIT#
(7)
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_D#[63:0]
H_D#[63:0]
Y2
E4
A[17]#
HITM#
H_HITM#
(7)
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#48
H_D#49
H_D#50
H_D#51
U5
N22
AE24
A[18]#
D[16]#
D[48]#
ITP_BPM#0
ITP_BPM#1
R3
AD4
K25
AD24
A[19]#
BPM[0]#
D[17]#
D[49]#
W6
AD3
P26
AA21
A[20]#
BPM[1]#
D[18]#
D[50]#
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
U4
AD1
R23
AB22
A[21]#
BPM[2]#
D[19]#
D[51]#
H_D#52
H_D#53
H_D#54
H_D#55
Y5
AC4
L23
AB21
A[22]#
BPM[3]#
D[20]#
D[52]#
U1
AC2
M24
AC26
A[23]#
PRDY#
D[21]#
D[53]#
R4
AC1
L22
AD20
A[24]#
PREQ#
D[22]#
D[54]#
ITP_TCK
ITP_TDO
T5
AC5
M23
AE22
A[25]#
TCK
D[23]#
D[55]#
ITP_TDI
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#56
H_D#57
H_D#58
H_D#59
T3
AA6
P25
AF23
A[26]#
TDI
D[24]#
D[56]#
W2
AB3
P23
AC25
A[27]#
TDO
D[25]#
D[57]#
ITP_TMS
W5
AB5
EB1213-0006
P22
AE21
A[28]#
TMS
D[26]#
D[58]#
ITP_TRST#
Y4
AB6
T24
AD21
A[29]#
TRST#
D[27]#
D[59]#
H_D#60
H_D#61
H_D#62
H_D#63
U2
C20
R24
AC22
A[30]#
DBR#
SYS_RST#
(16)
D[28]#
D[60]#
V4
L25
AD23
A[31]#
D[29]#
D[61]#
C
R495
R495
*0_4
*0_4
+1.05V
C
W3
T25
AF22
H_PROCHOT#
(33)
A[32]#
D[30]#
D[62]#
AA4
THERMAL
THERMAL
N25
AC23
A[33]#
D[31]#
D[63]#
AB2
L26
AE25
A[34]#
(7)
H_DSTBN#1
DSTBN[1]#
DSTBN[3]#
H_DSTBN#3
(7)
R33
R33
68_4
68_4
R403
1K/F_4
AA3
D21
M26
AF24
+1.05V
A[35]#
PROCHOT#
(7)
H_DSTBP#1
DSTBP[1]#
DSTBP[3]#
H_DSTBP#3
(7)
V1
A24
N24
AC20
(7)
H_ADSTB#1
H_THERMDA
(6)
(7)
H_DINV#1
H_DINV#3
(7)
ADSTB[1]#
THERMDA
DINV[1]#
DINV[3]#
B25
H_THERMDC
(6)
THERMDC
H_GTLREF
CPU_TEST1
CPU_TEST2
CPU_TEST3
CPU_TEST4
CPU_TEST5
CPU_TEST6
CPU_TEST7
COMP0
COMP1
COMP2
COMP3
R405
R405
27.4/F_4
27.4/F_4
A6
AD26
R26
(14)
H_A20M#
A20M#
GTLREF
COMP[0]
A5
C7
C23
MISC
MISC
U26
R406
R406
54.9/F_4
54.9/F_4
(14)
H_FERR#
FERR#
THERMTRIP#
PM_THRMTRIP# (8,14)
TEST1
COMP[1]
R404
2K/F_4
R420
R420
27.4/F_4
27.4/F_4
C4
D25
AA1
EB1213-0010
(14)
H_IGNNE#
IGNNE#
TEST2
COMP[2]
R419
R419
54.9/F_4
54.9/F_4
C24
Y1
TP3
TP3
TEST3
COMP[3]
H CLK
H CLK
D5
AF26
(14)
H_STPCLK#
TP105
TP105
STPCLK#
TEST4
C6
AF1
E5
(14)
H_INTR
TP122
TP122
H_DPRSTP#
(8,14,33)
LINT0
TEST5
DPRSTP#
B4
A22
A26
B5
(14)
H_NMI
CLK_CPU_BCLK
(3)
TP2
TP2
H_DPSLP#
(14)
LINT1
BCLK[0]
TEST6
DPSLP#
A3
A21
C3
D24
(14)
H_SMI#
SMI#
BCLK[1]
CLK_CPU_BCLK#
(3)
TP36
TP36
TEST7
DPWR#
H_DPWR#
(7)
B22
D6
(3)
CPU_BSEL0
BSEL[0]
PWRGOOD
H_PWRGD
(14)
Quard Core Only
Quard Core Only
B23
D7
(3)
CPU_BSEL1
BSEL[1]
SLP#
H_CPUSLP#
(7)
R96
R96
*51/F_4
*51/F_4
F6
D2
C21
AE6
+1.05V
(3)
CPU_BSEL2
PM_PSI#
(33)
TDI_1/RSV
RSVD[06]
BSEL[2]
PSI#
EB1213-0007
D3
TDO_2/RSV
Penryn Ball-out Rev 1a
Penryn Ball-out Rev 1a
ITP_BPM1#0
ITP_BPM1#1
ITP_BPM1#2
ITP_BPM1#3
N5
BMP_1#[0]/RSV
CPU_TEST2
R37
R37
*1K/F_4
*1K/F_4
M4
BMP_1#[1]/RSV
B2
TP117
TP117
BMP_1#[2]/RSV
AE8
BMP_1#[3]/VSS
CPU_TEST1
R40
R40
*1K/F_4
*1K/F_4
D8
DCLKPH_1/VSS
GTLREF_CTL
F8
ACLKPH_1/VSS
H_GTLREF2
D22
TP1
TP1
GTLREF_2/RSV
H_THERMDA2
H_THERMDC2
T2
TP47
TP47
THRMDA_1/RSV
V3
THRMDC_1/RSV
AA8
HFPLL_1/VSS
AC8
SPARE_1[4]/VSS
LE6B: Connect
to +VCORE
according to Intel DG
0429
B
AA7
B
+VCORE
BR1#/VCC
Penryn Ball-out Rev 1a
Penryn Ball-out Rev 1a
+1.05V
R102
R102
54.9/F_4
54.9/F_4
ITP_TCK
R98
R98
54.9/F_4
54.9/F_4
ITP_TRST#
R101
*51/F_4
R421
*54.9/F_4
R89
54.9/F_4
R90
54.9/F_4
R514
54.9/F_4
EB1213-0008
ITP_TDI
ITP_TMS
ITP_TDO
TP118
TP118
H_CPURST#
R108
R108
*1K/F_4
*1K/F_4
ITP_RST#
TP42
TP42
SYS_RST#
TP116
TP116
ITP_BPM#2
TP121
TP121
A
A
ITP_BPM#4
TP120
TP120
ITP_BPM#5
TP119
TP119
PROJECT : LE6
Quanta Computer Inc.
PROJECT : LE6
Quanta Computer Inc.
PROJECT : LE6
Quanta Computer Inc.
C165
*100P/50V_4
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Custom
Custom
Custom
PENRYN 1/2
Friday, May 02, 2008
PENRYN 1/2
Friday, May 02, 2008
PENRYN 1/2
Friday, May 02, 2008
2A
2A
2A
Date:
Date:
Date:
Sheet
Sheet
Sheet
4
4
4
of
of
of
34
34
34
5
4
3
2
1
 5
4
3
2
1
05
(3,6,8,11,12,13,14,15,16,17,18,20,22,24,25,26,27,29,30,31,32,33,34)
+3V
(3,4,7,8,10,11,14,17,29,32,33)
+1.05V
(11,14,15,17,26,29,32)
+1.5V
+VCORE
+VCORE
+VCORE
(29,33)
+VCORE
U24C
U24C
U24D
U24D
A7
AB20
VCC[001]
VCC[068]
A9
AB7
A4
P6
VCC[002]
VCC[069]
VSS[001]
VSS[082]
A10
AC7
A8
P21
VCC[003]
VCC[070]
VSS[002]
VSS[083]
A12
AC9
A11
P24
VCC[004]
VCC[071]
VSS[003]
VSS[084]
A13
AC12
A14
R2
VCC[005]
VCC[072]
VSS[004]
VSS[085]
A15
AC13
A16
R5
VCC[006]
VCC[073]
VSS[005]
VSS[086]
A17
AC15
A19
R22
VCC[007]
VCC[074]
VSS[006]
VSS[087]
A18
AC17
A23
R25
VCC[008]
VCC[075]
VSS[007]
VSS[088]
A20
AC18
AF2
T1
VCC[009]
VCC[076]
VSS[008]
VSS[089]
D
D
B7
AD7
B6
T4
VCC[010]
VCC[077]
VSS[009]
VSS[090]
B9
AD9
B8
T23
VCC[011]
VCC[078]
VSS[010]
VSS[091]
B10
AD10
B11
T26
VCC[012]
VCC[079]
VSS[011]
VSS[092]
B12
AD12
B13
U3
VCC[013]
VCC[080]
VSS[012]
VSS[093]
B14
AD14
B16
U6
VCC[014]
VCC[081]
VSS[013]
VSS[094]
B15
AD15
B19
U21
VCC[015]
VCC[082]
VSS[014]
VSS[095]
B17
AD17
B21
U24
VCC[016]
VCC[083]
VSS[015]
VSS[096]
B18
AD18
B24
V2
VCC[017]
VCC[084]
VSS[016]
VSS[097]
B20
AE9
C5
V5
VCC[018]
VCC[085]
VSS[017]
VSS[098]
C9
AE10
C8
V22
VCC[019]
VCC[086]
VSS[018]
VSS[099]
C10
AE12
C11
V25
VCC[020]
VCC[087]
VSS[019]
VSS[100]
C12
AE13
C14
W1
VCC[021]
VCC[088]
VSS[020]
VSS[101]
C13
AE15
C16
W4
VCC[022]
VCC[089]
VSS[021]
VSS[102]
C15
AE17
C19
W23
VCC[023]
VCC[090]
VSS[022]
VSS[103]
C17
AE18
C2
W26
VCC[024]
VCC[091]
VSS[023]
VSS[104]
C18
AE20
C22
Y3
VCC[025]
VCC[092]
VSS[024]
VSS[105]
D9
AF9
C25
Y6
VCC[026]
VCC[093]
VSS[025]
VSS[106]
D10
AF10
D1
Y21
VCC[027]
VCC[094]
VSS[026]
VSS[107]
D12
AF12
D4
Y24
VCC[028]
VCC[095]
VSS[027]
VSS[108]
D14
AF14
AA2
VCC[029]
VCC[096]
VSS[109]
D15
AF15
D11
AA5
VCC[030]
VCC[097]
VSS[029]
VSS[110]
D17
AF17
D13
VCC[031]
VCC[098]
VSS[030]
D18
AF18
D16
AA11
VCC[032]
VCC[099]
VSS[031]
VSS[112]
+1.05V
E7
AF20
D19
AA14
VCC[033]
VCC[100]
VSS[032]
VSS[113]
E9
D23
AA16
VCC[034]
VSS[033]
VSS[114]
E10
G21
D26
AA19
VCC[035]
VCCP[01]
VSS[034]
VSS[115]
E12
V6
E3
AA22
VCC[036]
VCCP[02]
VSS[035]
VSS[116]
E13
J6
E6
AA25
VCC[037]
VCCP[03]
VSS[036]
VSS[117]
E15
K6
E8
AB1
VCC[038]
VCCP[04]
VSS[037]
VSS[118]
+
E17
M6
E11
AB4
VCC[039]
VCCP[05]
VSS[038]
VSS[119]
C
C
E18
J21
E14
AB8
VCC[040]
VCCP[06]
VSS[039]
VSS[120]
E20
K21
E16
AB11
VCC[041]
VCCP[07]
VSS[040]
VSS[121]
F7
M21
E19
AB13
VCC[042]
VCCP[08]
VSS[041]
VSS[122]
+1.5V
F9
N21
E21
AB16
VCC[043]
VCCP[09]
VSS[042]
VSS[123]
F10
N6
E24
AB19
VCC[044]
VCCP[10]
VSS[043]
VSS[124]
F12
R21
F5
AB23
VCC[045]
VCCP[11]
VSS[044]
VSS[125]
F14
R6
AB26
VCC[046]
VCCP[12]
VSS[126]
F15
T21
F11
AC3
VCC[047]
VCCP[13]
VSS[046]
VSS[127]
F17
T6
F13
AC6
VCC[048]
VCCP[14]
VSS[047]
VSS[128]
F18
V21
F16
VCC[049]
VCCP[15]
VSS[048]
F20
W21
F19
AC11
VCC[050]
VCCP[16]
VSS[049]
VSS[130]
F2
AC14
VSS[050]
VSS[131]
AA9
B26
F22
AC16
VCC[052]
VCCA[01]
VSS[051]
VSS[132]
AA10
C26
F25
AC19
VCC[053]
VCCA[02]
VSS[052]
VSS[133]
AA12
G4
AC21
VCC[054]
VSS[053]
VSS[134]
AA13
AD6
G1
AC24
VCC[055]
VID[0]
CPU_VID0
(33)
VSS[054]
VSS[135]
AA15
AF5
G23
AD2
CPU_VID1
(33)
VCC[056]
VID[1]
VSS[055]
VSS[136]
AA17
AE5
G26
AD5
CPU_VID2
(33)
VCC[057]
VID[2]
VSS[056]
VSS[137]
AA18
AF4
H3
AD8
CPU_VID3
(33)
VCC[058]
VID[3]
VSS[057]
VSS[138]
AA20
AE3
H6
AD11
VCC[059]
VID[4]
CPU_VID4
(33)
VSS[058]
VSS[139]
AB9
AF3
H21
AD13
VCC[060]
VID[5]
CPU_VID5
(33)
VSS[059]
VSS[140]
AC10
AE2
H24
AD16
VCC[061]
VID[6]
CPU_VID6
(33)
VSS[060]
VSS[141]
AB10
J2
AD19
VCC[062]
VSS[061]
VSS[142]
AB12
J5
AD22
VCC[063]
VSS[062]
VSS[143]
AB14
AF7
J22
AD25
VCC[064]
VCCSENSE
VCCSENSE
(33)
VSS[063]
VSS[144]
AB15
J25
AE1
VCC[065]
VSS[064]
VSS[145]
AB17
K1
AE4
VCC[066]
VSS[065]
VSS[146]
AB18
AE7
K4
VSSSENSE
(33)
VCC[067]
VSSSENSE
VSS[066]
K23
AE11
VSS[067]
VSS[148]
Penryn Ball-out Rev 1a
Penryn Ball-out Rev 1a
R85
100/F_4
R88
100/F_4
K26
AE14
VSS[068]
VSS[149]
B
.
.
L3
AE16
B
VSS[069]
VSS[150]
L6
AE19
VSS[070]
VSS[151]
L21
AE23
VSS[071]
VSS[152]
L24
AE26
VSS[072]
VSS[153]
M2
A2
VSS[073]
VSS[154]
M5
AF6
VSS[074]
VSS[155]
M22
AF8
VSS[075]
VSS[156]
+VCORE
M25
AF11
VSS[076]
VSS[157]
N1
AF13
VSS[077]
VSS[158]
N4
AF16
VSS[078]
VSS[159]
N23
AF19
VSS[079]
VSS[160]
N26
AF21
VSS[080]
VSS[161]
P3
A25
VSS[081]
VSS[162]
AF25
VSS[163]
Penryn Ball-out Rev 1a
Penryn Ball-out Rev 1a
+1.05V
.
.
A
A
PROJECT : LE6
Quanta Computer Inc.
PROJECT : LE6
Quanta Computer Inc.
PROJECT : LE6
Quanta Computer Inc.
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Custom
Custom
Custom
PENRYN 2/2
Tuesday, April 29, 2008
PENRYN 2/2
Tuesday, April 29, 2008
PENRYN 2/2
Tuesday, April 29, 2008
1A
1A
1A
Date:
Date:
Date:
Sheet
Sheet
Sheet
5
5
5
of
of
of
34
34
34
5
4
3
2
1
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